1. Field of the Invention
The present invention relates to the field of integrated circuit chips including the integrated circuit chip package and more particularly to testing power distribution systems for integrated circuit chips including the integrated circuit chip package.
2. Description of the Related Art
When designing integrated circuit chips, one area of importance is the design of a core power distribution that delivers power to the integrated circuit chip (for the purposes of this disclosure, the use of the term integrated circuit chip includes a corresponding integrated circuit chip package). It is important to provide power to the integrated circuit chip via enough pins that the impedance of the core power distribution is not an issue for the performance of the integrated circuit. However, designing a core power distribution system with too many pins provides its own set of challenges. The pins are expensive to manufacture. Also, and the more pins, the greater the insertion force required to insert the integrated circuit chip into a respective socket. Also, a large number of pins also increases the manufacturing complexity of both the integrated circuit and the integrated circuit socket. Accordingly, it is desirable to have the fewest number of pins associated with the core power distribution system that does not effect the performance of the integrated circuit.
However, it is often difficult to assess the effectiveness of a core power distribution system that delivers power to an integrated circuit chip such as a processor. Direct measurement of voltage excursions on a die is possible but difficult. It is unclear whether the observed excursions are tolerable.
It is known to perform schmoos on core voltage and operating frequency for a system. A schmoo plot is a plot of symbols indicating a result over a range of operating conditions such as core voltage and requency.